The present invention generally relates to a device for decoding an instruction code, and more particularly to a device which decodes an instruction code to thereby generate data which can be applied to an apparatus such as an electron beam exposure apparatus. Further, the present invention is directed to a decode device which can continuously generate a series of extended data corresponding to an instruction code. The present invention is suitable for a decode device which supplies an electron beam exposure device with exposure data.
Referring to FIG. 1, there is illustrated an electron beam exposure apparatus. The illustrated electron beam exposure apparatus is made up of a host computer 200, a bus 210, a data management device 220, a segmented pattern generator 230, a digital-to-analog converter 240, an amplifier 250 and an electron beam exposure device 260. The host computer 200 supplies the data management device 220 with input data, which includes an instruction code which indicates the shape of a pattern to be drawn, a starting point of exposure and the size of the pattern. The input data cannot be applied directly to the exposure device 260, since it draws a pattern on a wafer by repeatedly projecting a variable rectangular shaped beam having a limited size. For this reason, the segmented pattern generator 230 divides the input pattern supplied from the data management device 220 into pattern segments. The data relating to the pattern segments in digital form is converted into a corresponding analog signal through the D/A converter 240. The converted analog signal is amplified through the amplifier 250, and supplied to the exposure device 260.
FIG. 2 is a block diagram of the segmented pattern generator 230 which serves as a decoder. The segmented pattern generator 230 includes a microprocessor 100, which is composed of an operation/comparison circuit 103 and a memory 104. The operation/comparison circuit 103 includes a plurality of registers such as registers RG1, RG2, RG3 and RG4 (only four registers are illustrated for the sake of simplicity), an arithmetic and logic unit (hereinafter simply referred to ALU) 101, and a program counter (PC) 102. The memory 104 stores a plurality of control codes (extended data), which are necessary for an exposure procedure and has a data form which can be executed by the exposure device 260.
FIG. 3 is a flowchart of an operation of the microprocessor 100 shown in FIG. 2. Referring to FIGS. 2 and 3, the operation/comparison circuit 103 is supplied with an instruction code indicating the shape of a pattern to be drawn, for example (step S1). The instruction code is one of the input data supplied from the data management circuit 220. Next, comparison data #1 and #2 are written in the registers RG1 and RG2 (step S2). The comparison data #1 and #2 are some of the input data supplied from the data management circuit 220, and include the exposure starting point and the size of the pattern to be drawn, for example. Then the ALU 101 extracts a specific bit (bits) contained in the instruction code therefrom (step S3). After that, the ALU 101 inputs the comparison data #1 and #2 from the registers RG1 and RG2, and compares them to thereby generate a bit code indicative of the comparison result (step S4). The generated bit code is supplied to the program counter 102, which determines the address of a data storage area of the memory 104 to be accessed in which data (control code) for calculating extended data is stored, by referring to the bit codes obtained in the just previous step and the step before the previous step (step S5). The process in step S5 is executed by a microprogram provided in the microprocessor 100, which is controlled by the program counter 102. The address calculated in step S5 is stored in the register RG4, which serves as an address register. The address in the register RG4 is supplied to the memory 104, which outputs the contents of the data storage area (control code) designated by the supplied address. The readout control code is temporarily stored in the register RG3 (step S6), and is then supplied to an external hardware device (not shown). Then the external hardware device executes a process corresponding to the control code. When the corresponding process is completed, the procedure returns to step S1. The sequence of steps S1 to S7 is repeatedly carried out a designated number of times that this sequence is to be repeatedly executed (S8).
It is now assumed that a trapezoid depicted in FIG. 1 is divided into three pattern segments labeled P1, P2 and P3, and that control codes (extended data) #3, #1 and #6 shown in FIG. 2 relate to the pattern segments P1, P2 and P3, respectively. First, address `2` is calculated and written in the address register RG4 by the ALU 101 using input data containing the instruction code and the comparison data #1 and #2 relating to the input data of the trapezoid. The corresponding control code #3 is read out from the memory 104, and supplied to the external hardware device through the register RG3 and an output port. Second, address `0` is calculated and stored in the address register RG4 by the ALU 101 using the input data. The corresponding control code #1 is read out from the memory 104, and supplied to the external hardware device. Third, address `5` is written in the address register RG4 by the ALU 101 using the input data. The corresponding control code #6 is read out from the memory 104, and supplied to the external hardware device.
The control codes (extended data) thus formed are supplied to the exposure device 260 (FIG. 1) through the D/A converter 240 and the amplifier 250.
However, the aforementioned conventional decoder has the following disadvantages. The microprocessor serving as the decoder is controlled by the microprogram addressed by the program counter 102. In case where a large number of decision making conditions is required for the comparison procedure in step S4, the operation executing cycle increases and thus it takes a long time to obtain the bit code indicative of the comparison result. In addition, the comparison data #1 and #2 must be transferred via the registers RG1 and RG2 and an accumulator (not shown for the sake of simplicity) provided in the operation/comparison circuit 103. Thus, the memory access is delayed.